In this paper, we use technology to reduce power gating Power consumption in 45nm SRAM Cell. We have compared the leakage current in normal conditions, reduce VM, increase the VSL, reduce VM simultaneously with increase in the case flow VSL provides 1V, 1.2V, 1.4V and 1.2 cases supply lines in the -27oC temperatures, 0 ° C, 27oC, 100oC. Achievements are reducing VM and increase VSLvoi 1V voltage supply is optimal.
And depending on the applications that are going to choose the specifications of Power geting technologies accordingly. For example, in SRAM applications used in devices with limited power supply (usually battery, solar cells ...) without the need for high speed response (mobile, sensors ... ) then we should use optimization techniques is to use both reduced and increased VSL VM. If as in the equipment on the need to add speed processors (such as smartphones, the information processing node concentration sensor ...), we can use the technique reduced or increased VM VSL (VSL to increase the not recommended because of high energy-consuming). But for other applications of SRAM as in the desktop PC, the device can handle direct supply (wifi modules, hubs, switches, devices need a high speed of response), we can use increase VSL techniques.
In the future, we may be researched more about the technical delay in 45nm technology, along with a deeper understanding of the factors affecting the SRAM Cell, learn techniques other reduced power consumption, the smaller 45nm technology, ...
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